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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
FEATURES
* One 3.3V or 2.5V LVPECL output pair * Two selectable crystal oscillator interfaces for the VCXO, one differential clock or one LVCMOS/LVTTL clock inputs * CLK1 and nCLK1 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Crystal operating frequency range: 14MHz - 24MHz * VCO range: 490MHz - 640MHz * Output frequency range: 40.83MHz - 640MHz * VCXO pull range: 100ppm (typical) * Supports the following applications (among others): SONET, Ethernet, Fibre Channel, HDTV, MPEG * RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.84 (typical) * Supply voltage modes: VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS813001I is a dual VCXO + FemtoClockTM Multiplier designed for use in Discrete PLL loops. HiPerClockSTM Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb Fibre Channel (106.25MHz system reference clock) modes. Of course, a multitude of other applications are also possible such as switching between 74.25MHz and 74.175824MHz for HDTV, switching between SONET, FEC and non FEC rates, etc.
ICS
The ICS813001I is a two stage device - a VCXO followed by a FemtoClockTM PLL. The FemtoClockTM PLL can multiply the crystal frequency of the VCXO up to a range of 40.83MHz to 640MHz, with a random rms phase jitter of less than 1 ps (12kHz - 20MHz). This phase jitter performance meets the requirements of 1Gb/10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48. The FemtoClockTM PLL can also be bypassed if frequency multiplication is not required. For testing/debug purposes, de-assertion of the output enable pin will place both Q0 and nQ0 in a high impedance state.
BLOCK DIAGRAM
VCO_SEL Pullup CLK_SEL0 Pulldown CLK_SEL1 Pullup CLK0 Pulldown Pulldown CLK1 nCLK1 Pullup
00 01 PD 1 0(default) VCO 490-640MHz
0
Output Divider N N2:N0 000 /1 001 /2 010 /3 011 /4 (default) 100 /5 101 /6 110 /8 111 /12
XTAL_IN0
1
Q0 nQ0
XTAL_OUT0
VCXO
XTAL_IN1
11
XTAL_OUT1
VC M2 Pullup M1 Pulldown M0 Pulldown N2 Pulldown N1 Pullup N0 Pullup O E Pullup
Feedback Divider M M2:M0 000 /16 001 /20 010 /22 011 /24 100 /25 (default) 101 /32 110 /40 111 Not Used
PIN ASSIGNMENT
VCO_SEL N0 N1 N2 VCCO Q0 nQ0 VEE VCCA VCC XTAL_OUT1 XTAL_IN1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK_SEL1 CLK_SEL0 OE M2 M1 M0 CLK1 nCLK1 CLK0 VC XTAL_IN0 XTAL_OUT0
ICS813001I
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 813001AGI www.icst.com/products/hiperclocks.html REV. A MARCH 30, 2005
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
Type Description VCO select pin. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19, 20 21 22 Name VCO_SEL N0, N1 N2 VCCO Q0, nQ0 VEE VCCA VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 VC CLK0 nCLK1 CLK1 M0, M1 M2 OE Input Input Input Power Ouput Power Power Power Input Input Input Input Input Input Input Input Input Pullup Pullup
Pullup Output divider select pins. Default value = /4. Pulldown LVCMOS/LVTTL interface levels. Output supply pin. Differential output pair. LVPECL interface levels. Negative supply pin. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. VCXO control voltage input. Pulldown LVCMOS/LVTTL clock input. Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pulldown Feedback divider select pins. Default value = /25. LVCMOS/LVTTL interface levels. Pullup Pullup
Output enable. When HIGH, the output is active. When LOW, the output is in a high impedance state. LVCMOS/LVTTL interface levels. 23 CLK_SEL0 Input Pulldown Clock select pin. Selects CLK0. LVCMOS/LVTTL interface levels. Clock select pin. When LOW, selects CLK1. When HIGH, selects nCLK1. 24 CLK_SEL1 Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. A MARCH 30, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
4.6V -0.5V to VCC + 0.5V 50mA 100mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VCC VCCA VCCO IEE ICCO Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 110 5 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VCC VCCA VCCO IEE ICCO Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 110 5 Maximum 3.465 3.465 2.625 Units V V V mA mA
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VCC VCCA VCCO IEE ICCO Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 105 5 Maximum 2.625 2.625 2.625 Units V V V mA mA
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V Minimum Typical 2.0 1.7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 5 -5 -150 Units V V V V A A A A
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage N2, M0, M1, CLK0, CLK_SEL0 N0, N1, M2, VCO_SEL, CLK_SEL1 N2, M0, M1, CLK0, CLK_SEL0 N0, N1, M2, VCO_SEL, CLK_SEL1
IIH
Input High Current
IIL
Input Low Current
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol IIH Parameter CLK1 Input High Current nCLK1 CLK1 IIL VPP Input Low Current nCLK1 Peak-to-Peak Input Voltage Test Conditions VIN = VCC = 3.465V or 2.625V VIN = VCC = 3.465V or 2.625V VIN = 0V, VCC = 3.465V or 2.625V VIN = 0V, VCC = 3.465V or 2.625V Minimum Typical Maximum 150 5 -5 -150 0.15 1.3 VCC - 0.85 Units A A A A V V
Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended appliations, the maximum input voltage for CLK1, nCLK1 is VCC + 0.3V.
TABLE 3E. LVPECL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Load NOTE: Characterized using an 18pF parallel resonant crystal.
813001AGI
Test Conditions
Minimum 14
Typical
Maximum 24 50 7 1
Units MHz MHz pF mW
Fundamental
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REV. A MARCH 30, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
Test Conditions VCO_SEL = 1 622.08MHz (12kHz - 20MHz) 490 TBD 20% to 80% 400 50 Minimum 40.83 0.84 640 Typical Maximum 640 Units MHz ps MH z ms ps %
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range PLL Lock Time Output Rise/Fall Time
tjit(O)
fVCO tL tR / tF
odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range PLL Lock Time Output Rise/Fall Time 20% to 80% Test Conditions VCO_SEL = 1 622.08MHz (12kHz - 20MHz) 490 TBD 370 50 Minimum 40.83 0.87 640 Typical Maximum 640 Units MHz ps MH z ms ps %
tjit(O)
fVCO tL tR / tF
odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT f IN Parameter Output Frequency Input Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range PLL Lock Time Output Rise/Fall Time 20% to 80% Test Conditions VCO_SEL = 1 Minimum 40.83 12.25 622.08MHz (12kHz - 20MHz) 490 TBD 370 50 1.2 640 Typical Maximum 640 40 Units MHz MHz ps MH z ms ps %
tjit(O)
fVCO tL tR / tF
odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
TYPICAL PHASE NOISE AT 622.08MHZ
0 -10 -20 -30 -40 -50
OC-12 Filter 622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.84ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-130 -140 -150 -160 -170 -180 -190 100 1k
Phase Noise Result by adding Sonet OC-12 Filter to raw data
10k
-120
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
PARAMETER MEASUREMENT INFORMATION
2V 2.8V0.04V 2V
Qx
VCC, VCCA, VCCO
SCOPE
VCC, VCCA
Qx
SCOPE
VCCO
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2V
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
VCC, VCCA, VCCO
Qx
SCOPE
V CC nCLK1
V
PP
LVPECL
CLK1
nQx
Cross Points
V
CMR
VEE VEE -0.5V 0.125V
2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
DIFFERENTIAL INPUT LEVELS
Q0 nQ0
Pulse Width t
PERIOD
Phase Noise Mask
odc =
Offset Frequency
t PW t PERIOD
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
80% Clock Outputs 80% VSW I N G 20% tR tF 20%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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PRELIMINARY
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS813001I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
813001AGI
BY
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REV. A MARCH 30, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION
FOR
3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813001I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS813001I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.15mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with output switching) = 381.2mW + 30mW = 411.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 70C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.411W * 65C/W = 111.7C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
24-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V
OH_MAX
=V
CC_MAX
- 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = V (V
CCO_MAX
OL_MAX
=V
CC_MAX
- 1.7V
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0 1
65C/W
2.5
62C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
TRANSISTOR COUNT
The transistor count for ICS813001I is: 3948
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Integrated Circuit Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL
Marking ICS813001AGI ICS813001AGI Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube tape & reel Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS813001AGI ICS813001AGIT
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 813001AGI
www.icst.com/products/hiperclocks.html
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REV. A MARCH 30, 2005

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